The goal of static timing analysis (STA) is to determine the latest and earliest possible switching times of various signals within a digital circuit. STA may generally be performed at the transistor level or at the gate level, using pre-characterized library elements, or at higher levels of abstraction, for complex hierarchical chips.
STA algorithms operate by first levelizing the logic structure, and breaking any loops in order to create a directed acyclic graph (timing graph). Modern designs can often contain millions of placeable objects, with corresponding timing graphs having millions, if not tens of millions of nodes. For each node, a corresponding arrival time, transition rate (slew), and required arrival time are computed for both rising and falling transitions as well early and late mode analysis. An arrival time (AT) represents the latest or earliest time at which a signal can transition due to the entire upstream fan-in cone. The slew value is the transition rate associated with a corresponding AT, and a required arrival time (RAT) represents the latest or earliest time at which a signal must transition due to timing constraints in the entire downstream fan-out cone.
AT's are propagated forward in a levelized manner, starting from the chip primary input asserted (i.e., user-specified) arrival times, and ending at either primary output ports or intermediate storage elements. For single fan-in cases,
AT sink node=AT source node+delay from source to sink.
Whenever multiple signals merge, each fan-in contributes a potential arrival time computed as
AT sink (potential)=AT source+delay,
making it possible for the maximum (late mode) or minimum (early mode) of all potential arrival times to be retained at the sink node. Typically an exact delay value for an edge in a timing graph is not known, but instead only a range of possible delay values can be determined between some minimum delay and maximum delay. In this case, maximum delays are used to compute late mode arrival times and minimum delays are used to compute early mode arrival times.
RATs are computed in a backward levelized manner starting from either asserted required arrival times at the chip primary output pins, or from tests (e.g., setup or hold constraints) at internal storage devices. For single fan-out cases,
RAT source node=RAT sink node−delay.
When multiple fan-outs merge (or when a test is present), each fan-out (or test) contributes a prospective RAT, enabling the minimum (late mode) or maximum (early mode) required arrival time to be retained at the source node. When only a range of possible delay values can be determined, maximum delay are used to compute late mode required arrival times and minimum delays are used to compute early mode required arrival times.
The difference between the arrival time and required arrival time at a node (i.e., RAT−AT in late mode, and AT−RAT in early mode) is referred to as slack. A positive slack implies that the current arrival time at a given node meets all downstream timing constraints, and a negative slack implies that the arrival time fails at least one such downstream timing constraint. A timing point may include multiple such AT, RAT, and slew values, each denoted with a separate tag, in order to represent data associated with different clock domains (i.e., launched by different clock signals), or for the purpose of distinguishing information for a specific subset of an entire fan-in cone or fan-out cone.
In addition to asserted required arrival times at primary outputs, designers may also specify maximum and minimum path delay constraints between pairs of nodes (a “from” node, and a “to” node) in the timing graph. These path delay constraints are called point-to-point delay constraints or point-to-point delay assertions. Such constraints may be required to ensure correct operation of asynchronous timing interfaces, or to measure the cumulative path delay (e.g., from a hard-core output to a chip primary output pin), or even as a guide to help enable delay/slack apportionment techniques during optimization.
Prior art approaches to the aforementioned problem are described, for instance, in U.S. Pat. No. 6,237,127 B1 to Craven et al., in which, a method for handling path-delay constraints is set forth either employing exhaustive path tracing between the source and sink points that is well-known to have exponential computational complexity, in order to ensure that all possible paths meet the required constraint or, alternatively, to rely upon inserting additional tags in the timing graph. Tags permit differentiating an arrival time and associated slew value at the “to” node due to signals propagated from the specified “from” node, from an arrival time and associated slew value at the “to” node due to all other signals. Similarly, tags permit differentiating a required arrival time “from” node due to signals propagated backward from the specified “to” node, from a required arrival time at the “from” node due to all other signals. In essence, with tags an independent STA is performed in parallel for each point-to-point constraint (i.e., once for each tag value). Due to its exponential complexity, the path tracing method is expensive to execute incrementally and is therefore not easily usable by automated optimization methods which make numerous changes to the timing graph in order to correct for timing, power, and/or noise violations. Even when used non-incrementally, application of such point-to-point assertions may be highly time consuming due to the need to identify all possible paths between specified from and to points. Methods which use additional tags may avoid the need for explicit path tracing and therefore can be incremental; however, these techniques typically incur a large memory and runtime overhead due to the need to introduce additional tagged timing values in the entire fan-out cone of the “from” node of every such point-to-point assertion, or at all points in the intersections of the fan-out cone of the “from” node and the fan-in cone of the “to” node of the point-to-point assertion. In particular, whenever such fan-out cones interact, multiple corresponding tags will propagate in the overlapping regions of fan-out. For each such tag, a unique version of AT/RAT/slew values is computed and stored, significantly increasing the memory overhead. Furthermore, since each tag has a different slew value, and delay and slew calculation for an edge in a timing graph generally depend on the slew at the source of that edge, a unique corresponding delay and sink slew calculation is required, increasing the runtime overhead as well.
To further appreciate the use of fan-out cones, a representative example is shown in FIG. 1, illustrating an instance where such a situation occurs. In the example, two point-to-point delay constraints are present. The first is between nodes “From #1” and “To #1”, and the second is between nodes “From #2” and “To #2”. Nodes A, B, C are in the fan-out cones of both “From #1” and “From #2” and unique tags for each of the two point to point constraint will propagate to each of the nodes A, B and C.
In another instance, e.g., in U.S. Pat. No. 5,825,658 to Ginetti et al., special timing constraints are specified, including multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements. Other constraints are based on timing path specifications, each indicating signal paths through the integrated circuit chip to which specified ones of multi-cycle timing constraints are applicable and signal paths to which the specified ones of the multi-cycle timing constraints are not. The system then verifies that the integrated circuit satisfies the specified timing constraints. The method is restricted to the stated special path constraints and propagation of timing information associated thereto.
Thus, there is a need in industry of a system and a method for performing STA in the presence of point-to-point delay constraints to minimize the need for exponential path tracing and/or the application of additional tags to the timing graphs.